Verilog, or HDL development for probabilistic computing with reconfigurable hardware. Our target applications include many computer vision applications.
Project Dates
Start Date: 1/11/2022 - End Date: 4/27/2022
Students Needed
Type of Project
Individual
Student Responsibilities
Mainly HDL programming, matlab programming.
Time Commitment
Student Requirements
Preferably UG in their third year or 4th year. Have taken FPGA or HDL class.
Interested in Working With the Following Programs
For EXCEL URE Students Only
Additional Notes